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stk14ec16 1 september, 2008 document control #ml0061 rev 1.2 this is a product in development that has fixed tar- get specifications that are subject to change pend- ing characterization results. simtek confidential & proprietary preliminary features ? 15, 25, 45 ns read access and r/w cycle time ? unlimited read/write endurance ? automatic non-volatile store on power loss ? non-volatile store under hardware or software control ? automatic recall to sram on power up ? unlimited recall cycles ? 200k store endurance ? 20-year non-volatile data retention ? single 3.0v +20%, -10% operation ? commercial, industrial temperatures ? 44-pin or 54-pin 400-mil tsopii packages (rohs- compliant ) ? 48-ball fine pitch ball grid array (fbga) description the simtek stk14ec16 is a 4mb fast static ram with a non-volatile quantum trap storage element included with each memory cell. the sram provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal sram. data transfers automatically to the non-volatile stor - age cells when power loss is detected (the st ore operation). on power up, data is automatically restored to the sram (the recall operation). both store and recall operations are also available under software control. the simtek nvsram is the highest performance, most reliable n on-volatile memory available. block diagram eeprom array 2048 x 2048 recall store/ recall control hsb power control store sram array 2048 x 2048 inp ut buf fers colum n i/o dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 e a0 - a15 software detect row decoder column decoder v cc v cap a9 a10 a11 a12 a13 a14 a15 a16 w g lb ub a0 a2 a3 a4 a5 a6 a7 a8 a17 a1 256kx16 autostore nvsram
2 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary x will be h or l operating mode e hsb w g lb ub dq0-dq7 dq8-dq15 standby/not selected h h x x x x high-z high-z internal read l h h h x x high-z high-z l h x x h h high-z high-z lower byte read l h h l l h data outputs low-z high-z upper byte read l h h l h l high-z data outputs low-z word read l h h l l l data outputs low-z data outputs low-z lower byte write l h l x l h data inputs high-z high-z upper byte write l h l x h l high-z data inputs high-z word write l h l x l l data inputs high-z data inputs high-z truth table for sram operations
stk14ec16 3 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary pin descriptions pin name i/o description a 17 -a 0 input address: the 18 address inputs select one of 262,144 words in the nvsram array dq 15 -dq 0 i/o data: bi-directional 16-bit data bus for accessing the nvsram e input chip enable: the active low e input selects the device lb input byte write select input: controls dq7-dq0 (unselected by te will not write or read). ub input byte write select input: controls dq15-dq8 (unselected byte will not write or read). w input write enable: the active low w enables data on the dq pins to be written to the address location latched by the falling edge of e g input output enable: the active low g input enables the data output buffers during read cycles. de-asserting g high causes the dq pins to tri-state. v cc power supply power: 3.0v +20%, -10% hsb i/o hardware store busy : when low this output indicates a store is in progress (also low during power up while busy). when pulled low external to the chip, it will initiate a non-volatile store op eration. a weak pull up resistor keeps this pin high if not c onnected. (connection optional). after each store operation, hsb will be driven high for a short time at the standard output high current (i out = - 2 ma). see note b. v cap power supply autostore capacitor: supplies power to the nvsram during a power loss to store data from sram to non-volatile stora ge elements. v ss power supply ground nc no connect this pin is not connected to the die. (do not connect in design; reserved for future use) 44-pin tsop-ii (see full mechanical drawings on pages 18 ? 20) 54-pin tsop-ii 48-ball fbga v ss a 0 a 1 a 2 a 3 a 4 a 5 dq 0 dq 1 v cc v cap dq 2 dq 3 a 6 a 7 a 8 nc nc a 17 a 16 a 15 a 14 a 13 g dq 7 dq 6 v ss v cc dq 5 dq 4 hsb a 12 a 11 a 9 nc nc nc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc a 10 e nc nc 23 24 25 26 27 w 54 53 52 51 50 49 48 47 46 45 ub lb dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 nc lb g a 0 a 1 a 2 nc dq 8 ub a 3 a 4 e dq 0 dq 9 dq 10 a 5 a 6 dq 1 dq 2 v ss dq 11 a 17 a 7 dq 3 v cc v cc dq 12 v cap a 16 dq 4 v ss dq 14 dq 13 a 14 a 15 dq 5 dq 6 dq 15 hsb a 12 a 13 w dq 7 nc a 8 a 9 a 10 a 11 nc 1 2 3 4 5 6 a b c d e f g h (top) (top) v ss a 2 a 3 a 4 a 5 dq 0 dq 1 v cc v cap dq 2 dq 3 a 6 a 7 a 8 a 1 a 17 a 16 a 15 a 14 a 13 dq 7 dq 6 v ss v cc dq 5 dq 4 a 12 a 11 a 9 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a 0 a 10 e w dq 8 dq 9 dq 10 dq 11 g dq 12 dq 13 dq 14 dq 15 ub lb (top)
4 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary absolute maximum ratings a voltage on input relative to ground . . . . . . . . . . . . . ?0.5v to 4.1v voltage on input relative to v ss . . . . . . . . . . ?0.5v to (v cc + 0.5v) voltage on dq 0-7 or hsb . . . . . . . . . . . . . . . . ?0.5v to (v cc + 0.5v) temperature under bias. . . . . . . . . . . . . . . . . . . . . .?55 c to 12 5 c junction temperature . . . . . . . . . . . . . . . . . . . . . . .?55 c to 14 0 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .?65 c to 15 0 c minimum accumulated storage time @ 1 50c am bient temperature. . . . . . . . . . . . . . . . 1000 hours @ 8 5 c ambient temperature. . . . . . . . . . . . . . . . . . . 20 years power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w dc output current (1 output at a time, 1s duration) . . . . . . . 15ma note a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at con - ditions above those indicated in the op erational sections of this specification is not implied. exposure to absolute maximum rat - ing conditions for extended periods may affect reliability. dc characteristics (v cc = 2.7v-3.6v) note b: the hsb pin has i out = -2 ua for v oh of 2.4 v when both active high and low drivers are disabled. when they are enabled, standard v oh and v ol are valid. symbol parameter commercial industrial units notes min max min max i cc 1 average v cc current 70 65 50 75 70 52 ma ma ma t avav = 15ns t avav = 25ns t avav = 45ns dependent on output loading and cycle rate. v a lues obtained without output loads. i cc 2 average v cc current during store 10 10 ma all inputs don?t care, v cc = max average current for duration of store cycle (t store ) i cc 3 average v cc current at t avav = 200ns 3v, 25c, typical 35 35 ma w (v cc ? 0.2v) all other inputs cycling at cmos levels dependent on output loading and cycle rate. v a lues obtained without output loads. i cc 4 average v cap current during auto store cycle 5 5 ma all inputs don?t care average current for duration of store cycle (t store ) i sb v cc standby current (standby, stable cmos levels) 5 5 ma e ( v cc -0.2v) all others v in 0.2v or (v cc -0.2v) standby current level after non-volatile cycle co mplete i ilk input leakage current 1 1 a v cc = max v in = v ss to v cc i olk off-state output leakage current 1 1 a v cc = max v in = v ss to v cc , e or g v ih v ih input logic ?1? voltage 2.0 v cc + 0.5 2.0 v cc + 0.5 v all inputs v il input logic ?0? voltage v ss ?0.5 0.8 v ss ?0.5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ? 2ma (except hsb ) b v ol output logic ?0? voltage 0.4 0.4 v i out = 4ma t a operating temperature 0 70 ?40 85 c v cc operating voltage 2.7 3.6 2.7 3.6 v 3.0v nominal v cap storage capacitance 61 180 61 180 f between v cap pin and v ss , 5v rated (nom. 68 f to 15 0 f +20%, - 10%) nv c non-volatile store operations 200 200 k data r data retention 20 20 years @ max ta package thermal characteristics - see website at http://www.simtek.com
stk14ec16 5 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary ac test conditions capacitance b (t a = 25 c, f = 1.0mhz) note c: these parameters are guaranteed but not tested. input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 3v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels . . . . . . . . . . . . . . . 1.5v output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 and 2 symbol parameter max units conditions c in input capacitance 7 pf v = 0 to 3v c out output capacitance 7 pf v = 0 to 3v figure 1 : ac output loading 577 ohms 30 pf 789 ohms 3.0v including scope and output fixture figure 2 : ac output loading for tristate specs (t hz , t lz , t wlqz , t whqz , t glqx , t ghqz ) 577 ohms 5 pf 789 ohms 3.0v including scope and output fixture
6 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary sram read cycles note d: w must be high during sram read cycles. note e: device is continuously selected with e and g both low, lb and ub select bytes read. note f: measured 200 mv from steady state output voltage. note g: hsb must remain high during read and write cycles. td #1: sram read cycle: address controlled c,d,f td #2: sram read cycle: e , g , lb , and ub controlled d,f no. symbols parameter stk14ec16-15 stk14ec16-25 stk14ec16-45 units td #1 td #2 alt. min max min max min max 1 t elqv t acs chip enable access time 15 25 45 ns 2 t avav d t eleh d t rc read cycle time 15 25 45 ns 3 t avqv e t avqv e t aa address access time 15 25 45 ns 4 t glqv t oe output enable to data valid 10 12 20 ns 5 t blqv byte enable to data valid 10 12 20 ns 6 t axqx e t oh output hold after address change 3 3 3 ns 7 t elqx t lz address change or chip enable to output active 3 3 3 ns 8 t ehqz f t hz address change or chip disable to output inactive 7 10 15 ns 9 t blqx byte enable to output active 7 10 15 ns 10 t glqx t olz output enable to output active 0 0 0 ns 11 t ghqz f t ohz output disable to output inactive 7 10 15 ns 12 t bhqz e byte enable to output inactive 7 10 15 ns 13 t elicch c t pa chip enable to power active 0 0 0 ns 14 t ehiccl c t ps chip disable to power standby 15 25 45 ns previous data valid output data valid address valid (3) (6) address data output t avav t avqv t axqx (2) address valid high impedance t elqv g output data valid (2) (1) (4) (7) (9) (5) standby address e lb , ub data output active i cc t elicch t ehiccl t blqx t blqv t glqx t elqx t glqv t eleh t ghqz (11) t bhqz (12) t ehqz (8) (10) (13) (14) ) (23 t ehax (3) t avqv (22) t avel
stk14ec16 7 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary sram write cycles note h: if w is low when e goes low, the outputs remain in the high-impedance state. note i: e or w must be v ih during address transitions. td #3: sram write cycle: w controlled g,h td #4: sram write cycle: e controlled g,h no. symbols parameter stk14ec16-15 stk14ec16-25 stk14ec16-45 units td #3 td #4 td #5 alt. min max min max min max 15 t avav t avav t avav t wc write cycle time 15 25 45 ns 16 t wlwh t wleh t wlbh t wp write pulse width 10 20 30 ns 17 t elwh t eleh t elbh t cw chip enable to end of write 15 20 30 ns 18 t blwh t bleh t blbh byte enable to end of write 15 20 30 ns 19 t dvwh t dveh t dvbh t dw data set-up to end of write 5 10 15 ns 20 t whdx t ehdx t bhdx t dh data hold after end of write 0 0 0 ns 21 t avwh t avbh t aw address set-up to end of write 10 20 30 ns 22 t avwl t avel t avbl t as address set-up time 0 0 0 ns 23 t whax t ehax t bhax t wr address hold after end of write 0 0 0 ns 24 t wlqz f, h t wz write enable to output disable 7 10 15 ns 25 t whqx t ow output active after end of write 3 3 3 ns address valid high impedance input data valid previous data t avav (15) t elwh (17) t blwh (18) t avwh (21) t wlwh (16) address data output data input e lb, ub w t avwl (22) t wlqz (24) t dvwh (19) t whqx (25) t whdx (20) t whax (23) input data valid high impedance address valid data input data output lb , ub w e address t avav (15) t avel (22) t eleh (17) t ehax (23) t bleh (18) t wleh (16) t ehdx (20) t dveh (19)
8 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary td #5: sram write cycle: l b , ub controlled g,h autostore ? /power-up recall note j: t hrecall starts when v cc rises above v switch note k: if an sram write has not occurred since the last non-volatile cycle, no internal store will occur. however, hsb will be driven low after t delay for the duration of t store . the part is disabled until after power-up recall is complete, then read and write operations can continue. td #6: autostore ?/power-up recall no. symbols parameter stk14ec16 units notes td #6 alternate min max 26 t hrecall power-up recall duration 20 ms j 27 t store t hlhz store cycle duration 8 ms k 28 v switch low voltage trigger level 2.65 v 29 t vccrise v cc rise time 150 s 30 v hdis hsb output driver disable voltage 1.9 v 31 v reset reset voltage 1.6 v 32 t pureh e hold time after power-up recall start 10 20 ms 33 t purhh hsb hold time after power-up recall start 70 s 34 t hhel e hold time after power-up recall completed 5 s input data valid t avbl t bhdx address e w data input data output t avav t blbh t bhax t wlbh t dvbh high impedance address valid t elbh lb , ub (15) (22) (17) (23) (18) (16) (19) (20) t avbh (21) t store (27) v cc v switch (28) t vccrise (29) t store (27) autostore power-up recall t hrecall (26) t hrecall (26) read & write inhibited power-up recall read & write brown out autostore power-up recall read & write power down autostore ** ** v ih e t pureh (32) hsb v hdis (30) v reset (31) t pureh (32) *** t delay (41) t delay (41) t hhel (34) t hhel (34) out t purhh (33) t hhhd (45) t hhhd (45) *** *** ** autostore occurs only if at least one sram write has occurred. *** hsb pin is driven high to vcc only by internal 100kohm resistor, hsb driver is disabled. read and write cycles are ignored during store, recall, e = high, and while v cc is below v switch .
stk14ec16 9 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary software-controlled store / recall cycle k.l note l: the software sequence is clocked on the falling edge of e controlled reads or g controlled reads note m: the six consecutive addresses must be read in the order listed in the software st ore/recall mode selection table. w must be high during all six consecutive e or g controlled cycles. td #7: software store / recall cycle: e & g controlled l no. symbols parameter stk14ec16-15 stk14ec16-25 stk14ec16-45 units notes td #7 k alternate min max min max min max 35 t avav t rc store / recall initiation cycle time 15 25 45 ns 36 t avel, t avgl t as address set-up time 0 0 0 ns 37 t eleh t cw clock pulse width 12 20 30 ns 38 t ehax, t ghax address hold time 1 1 1 ns l 39 t recall recall duration 200 200 200 s 40 t chclss ce hold time after soft sequence in 75 75 75 s dq (data) g e 35 t avav dv address address #1 high impedence 36 38 37 39 t recall 35 t avav address #6 27 t store data valid / t eleh 36 t avgl t avel t ehax hsb (store only) 41 t ghax t elqv 1 t ehqz 8 t eleh 37 t ehax 38 t delay t chclss 40 44 t hhqv 45 t hhhd
10 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary hardware store cycle note n: on a hardware store initiation, sram operation continues to be enabled for time t delay to allow read/write cycles to complete td #8: hardware store cycle soft sequence command td#9: soft sequence command symbols parameter stk14ec16 units notes td #8 alternate min max 41 t delay t hlqz hardware store to sram disabled 1 70 s n 42 t hlhx hardware store pulse width 15 ns 43 t hlha hardware store low to hardware stare active out 500 ns 44 t hhqv hsb to output active set up time 5 s 45 t hhhd hsb high active hold time 500 ns no. symbols parameter stk14ec16 units notes standard min max 46 t ss soft sequence processing time 70 s o.p hsb (out) hsb (in) 41 sram enabled 42 t hlhx sram enabled t delay 43 hlha t 45 hhhd t 44 hhqv t dq (data out) write latch not set hsb (out) hsb (in) 41 sram enabled 42 t hlhx sram enabled 27 t store t delay 43 hlha t 45 hhhd t 44 hhqv t dq (data out) note o: this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively register command. note p: commands like store and recall lock out i/o until operation is complete which further increases this time. see specific command.
stk14ec16 11 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary mode selection e w hsb g , ub , lb a 17 -a 0 mode i/o power notes h x x x x not selected output high z standby l h h l x read sram output data active l l h x x write sram input data active l h h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f 0x08b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active q,r,s l h h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f 0x04b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active q,r,s l h h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f read sram read sram read sram read sram read sram output data output data output data output data output data active q,r,s 0x08fc0 non-volatile store output high z i cc2 l h h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f 0x04c63 read sram read sram read sram read sram read sram non-volatile recall output data output data output data output data output data output high z active q,r,s note q: the six consecutive addresses must be in the order listed. w must be high during all six consecutive cycles to enable a non-volatile cycle. note r: while there are 18 addresses on the stk14ec16, only the lower 16 are used to control software modes note s: i/o state depends on the state of g, ub , and lb . the i/o table shown assumes g , ub , and lb low.
12 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary nvsram the stk14ec16 nvsram is made up of two func - tional components paired in the same physical cell. these are the sram memory cell and a non-volatile quantumtrap cell. the sram memory cell operates like a standard fast static ram. data in the sram can be transferred to the non-volatile cell (the store operation), or from the non-volatile cell to sram (the recall operation). this unique archi - tecture allows all cells to be stored and recalled in p arallel. during the store and recall operations sram read and write operations are inhibited. the stk14ec16 supports unlimited read and writes like a typical sram. in addition, it provides unlimited recall operations from the non-volatile cells and up to 200k store operations. sram read the stk14ec16 performs a read cycle whenever e and g are low while w and hsb are high. the address specified on pins a 0-17 determine which of the 262,144 data words will be accessed. byte enables ( ub , lb ) determine which bytes are enabled to the output. when the read is initiated by an address transition, the outputs will be valid after a delay of t avqv (read cycle #1). if the read is initiated by e and g , the outputs will be valid at t elqv or at t glqv , whichever is later (read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time with- out the need for transitions on any control input pins, and will remain valid until another address change or until e or g is brought high, or w and hsb is brought low. sram write a write cycle is performed whenever e and w are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on the common i/o pins dq0-15 will be written into memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write. the byte enable inputs ( ub , lb ) determine which bytes are written. it is recommended that g be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. autostore operation the stk14ec16 stores data to nvsram using one of three storage operations. these three operations are hardware store (activated by hsb), software store (activated by an address sequence), and autostore (on power down). autostore operation is a unique feature of simtek quantum t rap technology that is enabled by default on the stk14ec16. during normal operation, the device will draw cur - rent from v cc to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part will automatically disconnect the v cap pin from v cc . a store operation will be initiated with power provided by the v cap capacitor. figure 3 shows the proper connection of the storage cap acitor (v cap ) for automatic store operation. refer to the dc characteristics table for the size of the capacitor. the voltage on the v cap pin is driven to v cc by a regulator on the chip. a pull up should be placed on e to hold it inactive during power up. this pull-up is only effective if the e signal figure 3. autostore mode v cap v cc ce v cap 10k ohm 0.1f v cc nvsram operation
stk14ec16 13 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary is tri-state during power up. many mpu?s will tri-state their controls on power up. this should be verified when using the pullup. when the nvsram comes out on power-on-recall, the mpu must be active or the e held inactive until the mpu comes out of reset. to reduce unneeded non-volatile stores, autostore and hardw are store operations will not be executed unless at least one write operation has taken place since the most recent store or recall cycle. for autostore, however, hsb goes low for the duration of t store . software initiated store cycles are performed regardless of whether a write oper - ation has taken place. the hsb signal can be moni - tored by the system to detect an autostore cycle is in progress. hardware store ( hsb ) operation the stk14ec16 provides the hsb pin for control - ling and acknowledging the store operations. the hsb pin can be used to request a hardware store cycle. when the hsb pin is driven low, the stk14ec16 will conditionally initiate a store operation after t delay . an actual store cycle will only begin if a write to the sram took place since the last store or recall cycle. the hsb pin has a very resistive pullup and is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. this pin should be externally pulled up if it is used to drive other inputs. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the stk14ec16 will continue to allow sram operations for t delay . dur- ing t delay , multiple sram read operations beside any softsequences may take place. if a write is in progress when hsb is pulled low, or initiated after hsb is pulled low, but before t delay completes, it will be accepted as a valid sram write. however, any sram write cycles requested after t delay completes will be inhibited until hsb returns high. if the write latch is not set before t delay , hsb goes high after t delay . if hsb is not used, it should be left unconnected. hardware recall (power-up) during power up or after any low-power condition (v cc 14 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary cycle, the following sequence of e controlled or g controlled read operations must be performed: internally, recall is a two-step procedure. first, the sram data is cleared, and second, the non-vol - atile information is transferred into the sram cells. af ter the t recall cycle time, the sram will once again be ready for read or write operations. the recall operation in no way alters the data in the non-volatile storage elements.care must be taken so the controlling falling edge is glitch and ring free so as not to double clock the read address. data protection the stk14ec16 protects data from corruption dur - ing low-voltage conditions by inhibiting all externally initiate d store and write operations. the low- voltage condition is detected when v cc stk14ec16 15 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary low average active power cmos technology provides the stk14ec16 with the benefit of power supply current that scales with cycle time. less current will be drawn as the mem- ory cycle time becomes longer than 50 ns. only standby current is drawn when the chip is disabled. the overall average current drawn by the stk14ec16 depends on the following items: preventing autostore the autostore function can be disabled by initiating an autostore disable sequence. a sequence of read operations is perfo rmed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of e controlled or g controlled read operations must be performed: the autostore can be re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of e controlled or g controlled read operations must be performed: if the autostore function is disabled or re-enabled, a manual store operation (hardware or soft- ware) needs to be issued to save the autostore state through subsequent power down cycles. the part comes from the factory with autostore enabled, but best design practice is to set the enable or disable state during each power-up sequence and not depend on this factory default 1 the duty cycle of chip enable 2 the overall cycle rate for operations 3 the ratio of reads to writes 4 the operating temperature 5 the v cc level 6 i/o loading 1 read address 0x4e38 valid read 2 read address 0xb1c7 valid read 3 read address 0x83e0 valid read 4 read address 0x7c1f valid read 5 read address 0x703f valid read 6 read address 0x8b45 autostore disable 1 read address 0x4e38 valid read 2 read address 0xb1c7 valid read 3 read address 0x83e0 valid read 4 read address 0x7c1f valid read 5 read address 0x703f valid read 6 read address 0x4b46 autostore enable
16 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary ordering information stk14ec16-t f 45 i tr packing option blank = tube tr = tape and reel temperature range blank = commercial (0 to +70 c) i = industrial (-40 to +85 c) access time 15 = 15 ns 25 = 25 ns 45 = 45 ns lead finish f = nickel/palladium/gold (ni/pd/au) package t = plastic 44-pin 400 mil tsopii (32 mil pitch) u = plastic 54-pin 400 mil tsopii (32 mil pitch) b = plastic 48-pin fbga (fine pitch ball grid array)
stk14ec16 17 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary ordering codes part number description a ccess times temperature 2tk14ec16-tf15 3v 4m-16b autostore nvsram tsop44-400 15 ns access time commercial stk14ec16-tf15tr 3v 4m-16b autostore nvsram tsop44-400 15 ns access time commercial stk14ec16-tf25 3v 4m-16b autostore nvsram tsop44-400 25 ns access time commercial stk14ec16-tf25tr 3v 4m-16b autostore nvsram tsop44-400 25 ns access time commercial stk14ec16-tf45 3v 4m-16b autostore nvsram tsop44-400 45 ns access time commercial stk14ec16-tf45tr 3v 4m-16b autostore nvsram tsop44-400 45 ns access time commercial stk14ec16-uf15 3v 4m-16b autostore nvsram tsop54-400 15 ns access time commercial stk14ec16-uf15tr 3v 4m-16b autostore nvsram tsop54-400 15 ns access time commercial stk14ec16-uf25 3v 4m-16b autostore nvsram tsop54-400 25 ns access time commercial stk14ec16-uf25tr 3v 4m-16b autostore nvsram tsop54-400 25 ns access time commercial stk14ec16-uf45 3v 4m-16b autostore nvsram tsop54-400 45 ns access time commercial stk14ec16-uf45tr 3v 4m-16b autostore nvsram tsop54-400 45 ns access time commercial stk14ec16-bf15 3v 4m-16b autostore nvsram fbga48 15 ns access time commercial stk14ec16-bf15tr 3v 4m-16b autostore nvsram fbga48 15 ns access time commercial stk14ec16-bf25 3v 4m-16b autostore nvsram fbga48 25 ns access time commercial stk14ec16-bf25tr 3v 4m-16b autostore nvsram fbga48 25 ns access time commercial stk14ec16-bf45 3v 4m-16b autostore nvsram fbga48 45 ns access time commercial stk14ec16-bf45tr 3v 4m-16b autostore nvsram fbga48 45 ns access time commercial stk14ec16-tf15i 3v 4m-16b autostore nvsram tsop44-400 15 ns access time industrial stk14ec16-tf15itr 3v 4m-16b autostore nvsram tsop44-400 15 ns access time industrial stk14ec16-tf25i 3v 4m-16b autostore nvsram tsop44-400 25 ns access time industrial stk14ec16-tf25itr 3v 4m-16b autostore nvsram tsop44-400 25 ns access time industrial STK14EC16-TF45I 3v 4m-16b autostore nvsram tsop44-400 45 ns access time industrial STK14EC16-TF45Itr 3v 4m-16b autostore nvsram tsop44-400 45 ns access time industrial stk14ec16-uf15i 3v 4m-16b autostore nvsram tsop54-400 15 ns access time industrial stk14ec16-uf15itr 3v 4m-16b autostore nvsram tsop54-400 15 ns access time industrial stk14ec16-uf25i 3v 4m-16b autostore nvsram tsop54-400 25 ns access time industrial stk14ec16-uf25itr 3v 4m-16b autostore nvsram tsop54-400 25 ns access time industrial stk14ec16-uf45i 3v 4m-16b autostore nvsram tsop54-400 45 ns access time industrial stk14ec16-uf45itr 3v 4m-16b autostore nvsram tsop54-400 45 ns access time industrial stk14ec16-bf15i 3v 4m-16b autostore nvsram fbga48 15 ns access time industrial stk14ec16-bf15itr 3v 4m-16b autostore nvsram fbga48 15 ns access time industrial stk14ec16-bf25i 3v 4m-16b autostore nvsram fbga48 25 ns access time industrial stk14ec16-bf25itr 3v 4m-16b autostore nvsram fbga48 25 ns access time indu strial stk14ec16-bf45i 3v 4m-16b autostore nvsram fbga48 45 ns access time industrial stk14ec16-bf45itr 3v 4m-16b autostore nvsram fbga48 45 ns access time industrial
18 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary package diagrams 54-pin tsopii 5 0 0.0235 0.597 0.0160 0.406 0.396 10.058 0.404 10.262 0.047 1.194 0.039 0.991 0.016 0.400 0.012 0.300 ( ) 0.0315 (0.800) bsc 0.729 18.517 0.721 18.313 ( ) 0.150 0.0059 0.050 0.0020 base plane seating plane 0.004 (0.10) dim = inches dim = mm max min max min 1 27 28 54 pin 1 index top view ( ) 0.404 0.396 10.262 10.058 ( ) 0.470 0.462 11.938 11.735 ( 0.878 0.886 22.517 22.313 ) ( ) ) ( ) ( ) ( ) (
stk14ec16 19 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary 44-pin tsopii 5 0 0.0235 0.597 0.0160 0.406 ( ) ( ) 0.0396 10.058 0.0404 10.262 0.047 1.194 0.039 0.991 ( ) 0.016 0.400 0.012 0.300 ( ) 0.0315 (0.800) bsc 0.729 18.517 0.721 18.313 ( ) 0.150 0.0059 0.050 0.0020 ( ) base plane seating plane 0.004 (0.10) dim = inches dim = mm max min max min ( ) ( ) 0.404 0.396 10.262 10.058 ( ) 0.470 0.455 11.938 11.735 top view 22 23 44 1 pin 1 index
20 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary 48-ball fbga a b c d e f g h a b c d e f g h 6 5 4 3 2 1 1.875 0.75 3.75 6.00 0.10 b 2.625 0.75 5.25 10.00 0.10 a 0.15(4x) 1 2 3 4 5 6 a1 corner a1 corner 10.00 0.10 a 6.00 0.10 b 0.15c 0.25c // 0.53 0.05 0.21 0.05 seating plane c 0.36 120 max ?0.05 m c ?0.25 m ca b 00.30 0.05(48x) top view bottom view + ++ + +
stk14ec16 21 simtek confidential september, 2008 document control #ml0061 rev 1.2 preliminary document revision history rev date change 1.0 april 2007 moved to preliminary from advance information ? made clear that nominal supply is 3.3v, not 3.0v (range 2.7v to 3.6v) ? modified language on pin description of hsb and nc. ? changed isb from 1ma to 2ma. ? changed icc3 from 8ma to 26ma ? clarified description language of figure 3 ? clarified description language of software recall ? clarified description language of preventing autostore ? corrected typo on industrial temp range: -45 to -40 1.1 january 2008 made the following changes to the document ? page 1: revised block diagram ? page 3: added new 48 fbga information, bock diagram, and package diagram; added pin descriptions for pins e , lb , ub , and w . ? page 4: added thermal characteristics. in the dc characteristics table, revised values for i cc2 , i cc4 , i sb , v ih , and v cap ;and changed industrial max value of v cap to 180 and revised v cap notes. added ?(except hsb )? to notes for output logic ?1? voltage. ? page 6: in sram read cycles #1 & #2 table, revised description for t elqx and t ehqz and changed symbol #2 to t eleh for read cycle time; updated sram read cycle #2 timing diagram and changed title to add g controlled. ? page 7: in sram write cycles, added symbol #3. ? page 8: added new sram write cycle #3. in autostore/power-up recall table, changed max value for #27 (t store ) to 12.5. revised autostore/power-up recall section. ? page 9: in software-controlled store/recall cycle table, revised values for t recall ; revised the notes below the software-controlled store/recall cycle diagram. ? page 11: in mode selection table, changed column to a 17 -a 0 . in the values in this column, added a zero after each instance of ?0x?; changed autostore enable value to 0x04b46. ? page 12: in auto-store operation, deleted line about v cap pin being driven to 5v by a charge pump internal to the chip. also, added stefan's revised text (italics show revision): ?refer to the dc characteristics table for the size of the capacitor.? ? page 13: under hardware store (hsb ) operation, revised first paragraph to read ?the h sb pin has a very resistive pullup...? ? page 14: added best practices section. ? page 16: in ordering information, lead finish, replaced ?sn (matte tin) rohs compliant? with ?nickel/palladium/gold (ni/pd/au).? also, added ?b = plastic 48-pin fbga (fine pitch ball grid array)? to finish. ? page 17: in ordering codes, added ordering information for 48 fbga and added access times column.
22 simtek confidential september, 2008 document control #ml0061 rev 1.2 stk14ec16 preliminary simtek stk14ec16 datasheet, september 2008 copyright 2008, simtek corporation. all rights reserved. this datasheet may only be printed for the expressed use of simtek customers. no part of the datasheet may be reproduced in any othe r form or means without the express written permission from simtek corporation. the information contained in this publication is believed to be accurate, but changes may be made without notice. simtek does not assume responsibility for, or grant or imply any warranty, including mer - chantability or fitness for a particular purpose regarding this information, the product or its use. simtek products are not wa r - ranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with simtek. furthermore, simtek does not authorize its products for use as critical components in life-suppo rt systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of simtek products in life- support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies simtek again st all charges. nothing herein constitutes a license, grant or transfer of any rights to any simtek patent, copyright, trademark, or o ther proprietary right. 1.2 september 2008 ? page 2: added footnote below truth table. ? page 4:add store time at max store temperature, update i cc2 to 10ma, i cc3 to 35ma, - i cc4 to 5ma, i sb to 5ma,v cap max to 180f, data r to max t a , ? page 6: added lb and ub to sram read cycle #2. ? page 7: added ?time? to no. 22 in the sram write cycles #1, #2, and #3 table. ? page 8: added ?time? to nos. 30, 31, 32, 33, and 34 in autostore/power-up recall cycle.also, updated t store to 8ms. ? page 9: updated parameter for no. 35 in the software-controlled store/recall cycle table. updated software store/recall cycle: e & g controlled figure. ? page 10: revised hardware store cycle and soft sequence command figures. ? page 11: mode selection: added a column for hsb . ? page 12: updated figure 3, autostore mode and autostore operation, fourth paragraph. ? page 13: hardware store ( hsb ) operation: reworded second paragraph. ? page 15: removed figure 4. ? page 18: corrected positioning of min and max in 44pin tsopii figure.

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